This application claims benefit of priority under 35 USC 119 based on Japanese patent application P2000-57492 filed Mar. 2nd, 2000, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to an integrated circuit such as LSI (Large-Scale Integration) including macro cells, more particularly, to a method of layout for the integrated circuit including macrocells.
2. Description of Related Art
FIG. 1 illustrates a layout of an LSI including macrocells in related art. A macrocell A comprises a circuit area 23 that is an area that has a circuit or circuits, and a non-circuit area 7 that is an area that has no circuits. In prior art, this macrocell A is treated as a macrocell that terminal group 1 extends to an upper side 3 and terminal group 2 extends to a right side 4.
In the layout of integrated circuits using macrocell A, the quadrilateral area defined as the macrocell A is treated as a wiring prohibition area for wiring layer used in macrocell A.
In this way, the area 7 is treated as a wiring prohibition area. Then, macrocell B is placed the area 7 closed to, but not overlapped with, the vertex 5 of the macrocell A and wires 8 and 9 are placed between macrocell A and B.
However, the number of the wiring in the interval of vertex 5, top right of the macrocell A and vertex 6, bottom left of the macrocell B drops sharply compared with the case the area 7 is treated as a wiring area. Therefore, the interval of the macrocell B and the macrocell A had to be wider than the necessity, and there was a problem of increase in the layout area of the LSI.
FIG. 2 illustrates another layout of an LSI including macrocells in related art. There are macrocell A same as macrocell A shown in FIG. 1 and macrocell B placed in the right as shown in FIG. 2. The right side 4 of the macrocell A and the left side 22 of the macrocell B have terminals 11 and 12. Wires 14 connected to the terminals 11 and 12 are wired at the area between the macrocell A and the macrocell B.
In this case, wires 13 connected to the terminals 10 of the macrocell A need to be wired via the area between the macrocell A and the macrocell B since the area 7 are treated as a wiring prohibition area. Furthermore, the interval between the macrocell A and the macrocell B needs to wider than the case that the area 7 is treated as a wiring area since the wirings 13 are wired at the area between the macrocell A and the macrocell B. In this way, there was a problem of increase in the layout area of the LSI.
A technique that wiring channels are formed in the vacant spaces in the macrocells is disclosed (Japanese patent laid open publication No. 5-259283). However the macrocell according to the technique is a quadrilateral per se. And the wiring channels are formed in advance. They may be designed at the same time of design of the macrocells. In this way, the vacant area cannot be used freely at the time of the LSI design stage.
Furthermore, a technique that basic cell arrays are formed in the vacant spaces in the macrocells is disclosed (Japanese patent laid open publication No. 9-008142). However the macrocell according to the technique is a quadrilateral per se. And the basic cell arrays are formed in advance. They may be designed at the same time of design of the macrocells. In this way, the vacant area cannot be used freely in the LSI design stage.
The present invention is to provide an integrated circuit, a macrocell and layout method for an integrated circuit capable of reduction in chip area using an area in macrocells.
The macrocell according to the invention has concavity-shaped, and an integration circuit of the present invention includes a concave macrocell. The concave macrocell includes macrocells that is hollowed-shape, macrocells that has a recess. Macrocells are a kind of cells used in standard cells. Generally, macrocells has same functions as multiple cells. Macrocells are often used in the shape of a quadrilateral so that these macrocells include non-circuit areas that are areas that do not have circuits. The non-circuit area in an integrated circuit is efficiently used according to this invention, so that the reduction in chip area can be realized by using the integrated circuit including the macrocell. On the other hand, the reduction in chip area can be realized that the non-circuit areas are treated as free areas for wiring or placing cells.
A method of layout integrated circuit includes a step for input a macrocell, a step for searching for non-circuit area in the macrocell, a step for replacing the macrocell with a macrocell excluded the free areas, and a step for layout an integrated circuit using the macrocell.
According to this invention, non-circuit areas in the macrocell are treated as free areas so that necessary wiring can be carried out even intervals between macrocells are narrowed.